By Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund
The promising excessive facts price instant functions at millimeter wave frequencies commonly and 60 GHz particularly have won a lot recognition in recent times. notwithstanding, demanding situations regarding circuit, format and measurements in the course of mm-wave CMOS IC layout must be triumph over ahead of they could develop into potential for mass market.60-GHz CMOS Phase-Locked Loops concentrating on phase-locked loops for 60 GHz instant transceivers elaborates those demanding situations and proposes strategies for them. The approach point layout to circuit point implementation of the whole PLL, in addition to separate implementations of person elements resembling voltage managed oscillators, injection locked frequency dividers and their mixtures, are incorporated. additionally, to meet a couple of transceiver topologies concurrently, flexibility is brought within the PLL structure through the use of new dual-mode ILFDs and switchable VCOs, whereas reusing the low frequency elements on the comparable time.
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Additional info for 60-GHz CMOS Phase-Locked Loops
For instance, the measurement cables may be coaxial while the wafer has micro-strip or coplanar waveguide based transmission lines carrying the RF sign-als. The selection of the probe, based on operating frequency range and layout of the chip is an important factor as incorrect probes can introduce losses degrading the overall measurements. The probe position and alignment (in z-direction) on the bond-pads is critical for correct mm-wave measurements especially during calibration and de-embedding procedures (explained in next section).
These currents, called eddy currents, cause power loss which appears as an effective increase in the series resistance of inductors. For frequencies lower than 10 GHz and moderately conductive substrates, the induced eddy currents are small and can be neglected. However, this is not the case as the operation frequency moves into the mm-wave regime. Consequently, realizing high quality-factor (Q) inductors, which is already a challenge at frequencies in excess of 10 GHz, becomes even more demanding due to the substrate induced losses.
This approach can be hazardous for mm-wave circuit layouts due to the resulting coupling. In this work, the above mentioned ground meshing is extensively utilized in the un-used chip areas to fulfill the density requirements as it includes all metal layers and contacts. Furthermore, the automatic tiling is blocked for sensitive RF paths and components and dummy metals are placed manually to avoid coupling and performance degradation. l The small dimensions of mm-wave ICs imply that the measurement probes are in close proximity to each other resulting in cross-talk.
60-GHz CMOS Phase-Locked Loops by Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund